If you’re new to DO-254, and you’re reading the document you will stumble upon multiple references to a Top-Level Drawing.

In the discussion of Detailed Design Data, you will be asked to create a Top-Level Drawing. The cryptic description in is:

“The top-level drawing uniquely identifies the hardware item and identifies all assemblies,
subassemblies, components and relevant documentation that define the hardware item


You might search for more information, but guess what? That’s it. That’s what it says. No further description. This will likely leave you scratching your head. How are you supposed to create a “drawing” of an FPGA? And no, a little black box will not do!

In the past, if you wanted to understand this further, you usually had to ask someone in the know (if you could find someone) or even pay a consultant. So frustrating. Why is this?

First, a little history may be helpful. Back in the day when DO-254 was first created (in the mid-to-late 1990s) the hardware that engineers were designing really could be drawn. People were designing simple boards with simple discrete components and the scope of DO-254 was supposed to encompass this. The drawing in that context would make sense. But fast forward to today when what you are likely doing is programming chips with millions of switches and circuits, and possibly built in processors, and suddenly that terminology makes little sense.

While the idea of a “drawing” doesn’t really hold, the purpose does. What you need to do is identify all the contents of the hardware item you are creating (that is undergoing DO-254 compliance) along with the environment in which it is developed. Thankfully the latest policy documents have clarified this a bit. Most noteworthy is AMC 20-152A[1], which states this in its DO-254 clarifications section 5.10:

“The Top-Level Drawing referenced in ED-80/DO-254 Appendix A corresponds to a

Hardware Configuration Index (HCI) document. The HCI document completely identifies

the hardware configuration, the embedded logic, and the development life-cycle data.

To support consistent and accurate replication of the custom device (ED-80/DO-254

Section 7.1), the Top-Level Drawing includes the hardware life cycle environment or

refers to a Hardware Environment Configuration Index (HECI) document.”

That’s a little more clear. Here’s a little more information. The HCI (often combined with the HECI) needs to include a description of the HW item that includes the source files and revision history, the hardware environment in which its built, and all the procedures to build the files into an implementation of the design that’s loaded into the target FPGA device. Oh and don’t forget all the data items (you know, that massive amount of documentation) that has been created during the life cycle alongside the design itself. The combination of ALL this information is “The Top-Level Drawing.” AMC 20-152A expands upon this in Appendix B (which adds some clarity to various aspects of DO-254) in Section B.2.1.1. So that’s a great place to refer to the next time you need to develop the Top-Level Drawing for your hardware.

If you want to learn more about the latest policy in AC/AMC 20-152A, take our FREE training here.

Also check out all the policy documents, including AC 20-152A, AC 00-72 and AMC 20-152A in our free Policy Documents area of our website.

[1] Note: This info is also found in the combination of AC 20-152A and AC 00-72.